ISA (IBM Standard Architecture)
- connects only to a card that has an 8-86,186 or 286 processor, and in which the processor addressing and IBM PC architecture addressing limitations.
- ISA Bus memory in two ranges: 640kb to 1MB or 15MB to 16MB.
- The instruction set provides 64k I/O, the ISA ignores A10 to A15 addresses and therefore only 1024 I/O port addresses are available.
- EISA (Extended ISA) works for 32 bit data and address lines version of ISA.
PCI and PCI-X Buses
- Peripheral Component Interconnect
- Platform Independent (Connects to any architecture and not like ISA)
- PCI provides three types of synchronous parallel interfaces a) 32/33 MHz b) 64/66MHz and PCI-X supports 64/100MHz
Later two super speed versions of PCI have been introduced
- PCI Super – 264/528 MBps at 3.3V on a 64 bit bus
- PCI Super – 132/264 Mbps on a 32 bit bus
- PCI-X Super – 800 MBps on a 64 bit bus at 3.3V
Is a high-integrity serial data communications bus for real-time control applications
Operates at data rates of up to 1 Mega bits per second
Was originally developed for use in cars, Is now being used in many other industrial automation and control applications
Fields in a CAN Frame
A Start of Frame (SOF) field – which indicates the beginning of a message frame.
An Arbitration field, containing a message identifier and the Remote Transmission Request (RTR) bit. The RTR bit is used to discriminate between a transmitted Data Frame and a request for data from a remote node.
A Control Field containing six bits:
A Standard CAN Frame consists of seven different bit fields:
* two reserved bits (r0 and r1) and
* a four bit Data Length Code (DLC). The DLC indicates the number of bytes in the Data Field that follows
A Data Field, containing from zero to eight bytes.
The CRC field, containing a fifteen bit cyclic redundancy check code and a recessive delimiter bit
The ACKnowledge field, consisting of two bits. The first is the Slot bit which is transmitted as recessive, but is subsequently over written by dominant bits transmitted from any node that successfully receives the transmitted message. The second bit is a recessive delimiter bit
The End of Frame field, consisting of seven recessive bits.
Following the End Of Frame is the INTermission field consisting of three recessive bits
The rate of data transmission depends on the total overall length of the bus and the delays associated with the transceivers. For all ISO11898 compliant devices running at 1Mbit/sec speed, the maximum possible bus length is specified as 40 Metres, For longer bus lengths it is necessary to reduce the bit rate. To give some indication of this the following numbers are from the DeviceNet features list:
500 K bits per second at 100 metres (328 ft)
250 K bits per second at 200 metres (656 ft)
125 K bits per second at 500 metres (1640 ft)
Inter Integrated Circuits (I2C)
- two-wired bus originally to interact within small num. of devs (radio/TV tuning, …)
– 100 kbps (standard mode)
– 400 kbps (fast mode)
– 3.4 Mbps (high-speed mode)
- data transfers: serial, 8-bit oriented, bi-directional
- master/slave relationships with multi-master option (arbitration)
- master can operate as transmitter or receiver
- addressing: 7bit or 10bit unique addresses
– serial data line (SDA)
– serial clock line (SCL)
USB is a device that can be attached, configured and used, reset, reconfigured and used, share the bandwidth with other devices, detached (while others are in operation) and reattached
- Developed by Intel, Microsoft and Philips in 1998.Initial model was USB 1.0.
- The latest version is USB 2.0.
- Currently supported versions are USB 1.1 and 2.0
- The Speed of USB 1.1 is(1.5Mbps or 12 Mbps)
- The speed of USB 2.0 is 480Mbps.
- USBs are bus powered or self powered.
- USBs are hot pluggable (once they are installed, there is no need for rebooting the system).
- USBs share their bandwidth.
- 127 USB devices can be connected to a single USB slot and all the devices shares the bandwidth.
- USBs has four wires, one for +5v, one for ground and two for twisted pair cables.
- The next version under research is USB3.0, the speed of it may be around 4.8Gbps.
- Timers are there to count the internal clock Pulses of a Micro controller.
- Counters are there to count the external pulses.
States of a Timer
- Initial State
Uses of a Timer
- Event driven(initiate an event after a delay)
- Scheduling of Tasks in a System (by activating and running a timer)
- Watchdog Timer (Resets the system after a predefine time)
- Real Time clock (A clock that never stops and keeps on running and never be reset, Eg. Heart Beat)
- Time slicing of various tasks.
There are two types of timer
- Atleast one hardware should be available in a Microcontroller.
- The figure above shows the Hardware Timer has the control bits
- Timer Enable
- Timer Start
- Timer Stop
- Pre scaling bits
- Up count enable
- Down count disable
- Load Enable
- Timer Interrupt Enable
Some Examples of IO Devices
Serial Input devices: Audio/video input, dial tone in a telephone
Serial Output Devices : Audio/Video Output, Dialing a Number
Serial UART Input: Modem, Keyboard, Keypad, Mouse
Serial UART Output: Modem, printer
Parallel Port Single bit input: Filling a liquid up to a fixed level
Parallel Port Single bit output: Pulses to an External Circuit
Parallel port Input: Encoder inputs for bits for angular position of a shaft
Parallel Port Output: Printer driving output bits
Serial Devices operates in three modes
When a byte or frame is transmitted at a constant time interval with uniform phase difference, then the transmission is said to be synchronous
Examples: Frames sent over a Local Area network.
Here byte or frame is transmitted at random time intervals
It is a special case where the max time interval can be varied
Von Newman Architecture
Direct Memory Access (DMA)
DMA is a circuit that can read data from an I/O Device and then write it into memory. In general, the IO Devices accessing the Memory with least bothering the processor.
The IO Devices request the DMAREQ and then the DMA Controller requests the BUSREQ from the processor. Once the processor gives back the BUSACK, the IO Device is ready to write to the memory or read from the memory. During the initiation of the BUSACK from the Processor, the Processor also places the Address on to which the data is to be written to the memory. Most of modern high end controllers or processors will be having the DMA controller in built in it.