4 bit Magnitude Comparator

Requirements:

  • WARP
  • Active HDL
  • Cool Runner and Fitter CPLD Kit

 

Program for Magnitude Comparator
library IEEE;
use IEEE.std_logic_1164.all;
entity mag_comp is
port (
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
eq: out STD_LOGIC;
agr: out STD_LOGIC;
bgr: out STD_LOGIC
);
end mag_comp;
architecture mag_comp of mag_comp is
begin
process(a,b)
begin
eq <= ‘0’;
agr <= ‘0’;
bgr <= ‘0’;
if (a=b) then
eq <= ‘1’;
elsif(a>b) then
agr <= ‘1’;
elsif(b>a) then
bgr <= ‘1’;
end if;
end process;
end mag_comp;

Symbol

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Waveform

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Bin Packing Assignment algorithm for EDF Scheduling

  1. This algorithm is for independent preemptible tasks.
  2. All the processors are identical. The tasks requires no resources except the processor time
  3. The period is equal to the relative deadline.
  4.  

    The sum of utilisations of the tasks assigned to a processor is always less than or equal to 1, the task set is EDF scheduled in that processor.

    So, the problme reduces to making task assignments with the property that the sum of the utilisations of the tasks assigned to a processor does not exceed to 1.

     

     

    T1

    T2

    T3

    T4

    T5

    T6

    T7

    T8

    T9

    T10

    T11

    ei

    5

    7

    3

    1

    10

    16

    1

    3

    9

    17

    21

    Pi

    10

    21

    22

    24

    30

    40

    50

    55

    70

    90

    95

    u(i)

    =ei/Pi

    0.50

    0.33

    0.14

    0.04

    0.33

    0.40

    0.02

    0.05

    0.13

    0.19

    0.22

     

    Arrange the tasks in the order of their utilisation

     

    So the order will be L={T1,T6,T2,T5,T11,T10,T3,T9,T8,T4,T7}

     

    Tasks

    u(i) -> utilisation

    Processor pi

    Assignment Vector(U)

    T1

    0.50

    p1

    (0.50)

    T6

    0.40

    p1

    (0.90)

    T2

    0.33

    p2

    (0.90, 0.33)

    T5

    0.33

    p2

    (0.90,0.66)

    T11

    0.22

    p2

    (0.90,0.88)

    T10

    0.19

    p3

    (0.90,0.88,0.19)

    T3

    0.14

    p3

    (0.90,0.88,0.33)

    T9

    0.13

    p3

    (0.90,0.88,0.46)

    T8

    0.05

    p1

    (0.95,0.88,0.46)

    T4

    0.04

    p1

    (0.99,0.88,0.46)

    T7

    0.02

    p2

    (0.99,0.90,0.46)

     

     

    Steps

  5. When T1 is scheduled, there is only one processor with utilisation 0.5, so T1 is allocated to p1
  6. When T6 comes, again p1 can accommodate as 0.5+0.4=0.9 which is again less than total utilisation factor 1.
  7. When T2 comes, its utilisation is 0.33 which cant be added to p1 since it will cross 1, so a new processor is added and it is p2.
  8. Like wise all other tasks are scheduled according to their utilisation factor.
  9.  

    The Final schedule is given below

    p1=> T1, T6,T8,T4

    p2=> T2,T5,T11,T7

    p3 => T10,T3,T9

     

Next fit Algorithm for RM Scheduling

  1. This algorithm uses the same assumptions used in the Rate Monotonic Scheduling
  2. This algorithm is based on the RM Scheduling algorithm for each processors
  3. The multi processor is assumed to consists of identical processors.
  4. The tasks are assumed to require no resources other than the CPU Time
  5.  

    The tasks are allocated to processors according to the classes in which they belong. Each classes contains a set of processors that is only allocated the tasks of that class.

     

    Tasks are allocated one by one to the appropriate processor classes until all the tasks have been scheduled.

    If any class fails to produce a feasible RM Schedule, then a new processor will be added to the same class and the corresponding task (which does not meets its deadline) is allocated to the new processor class.

     

    Example

    Let us say M=4 classes. The following table lists the classes

    Class

    Bound

    C1

    (0.41,1]

    C2

    (0.26,0.41]

    C3

    (0.19,0.26]

    C4

    (0, 0.19]

     

    The tasks sets are given below

     

    T1

    T2

    T3

    T4

    T5

    T6

    T7

    T8

    T9

    T10

    T11

    ei

    5

    7

    3

    1

    10

    16

    1

    3

    9

    17

    21

    Pi

    10

    21

    22

    24

    30

    40

    50

    55

    70

    90

    95

    u(i)=ei/Pi

    0.50

    0.33

    0.14

    0.04

    0.33

    0.40

    0.02

    0.05

    0.13

    0.19

    0.22

    Class

    C1

    C2

    C4

    C4

    C2

    C2

    C4

    C4

    C4

    C4

    C3

     

    Steps

  6. Since C1 class contains only one task T1, it will be RM Schedulable, so p1 is a processor under C1
  7. C2 contains three tasks, T2, T5 and T6, upon RM Scheduling T6 fails to meets its deadline, so a new processor is added to class C2. So class C2 contains two processors p2 and p5
  8. C3 is also having only one Task T11 and it will also be schedulable under RM, so p3 is a processor under C3.
  9. C4 contains 6 tasks namely, T3,T4, T7,T8,T9 and T10. All the tasks meets their deadlines under RM Scheduling, so p4 is a processor under C4
  10.  

    Processor

    Tasks

    p1

    T1

    p2

    T2, T5

    p3

    T11

    p4

    T3,T4,T7,T8,T9,T10

    p5

    T6

     

     

Priority Inheritance Protocol

    The use of Priority inheritance allows to avoid the priority inversion problem.

     

    Under this scheme, if a high priority task T1 is blocked by a lower priority task T2 (because T2 is currently executing a critical section needed by T1), the lower priority task temporarily inherits the priority of T1. When the blocking stops, T2 resumes its original priority.

     

  1. If a task T1 is blocked by T2 (due to contention for a critical section) and The priority of T1 is greater than T2, task T2 inherits the priority of T1 as long as it blocks T1. when T2 exits the critical section, it reverts to its original priority .
  2.  

  3. Priority inheritance is transitive. If T3 blocks, which blocks T1(with T1 being the highest priority, T2 the medium priority and T3 being the lower priority), then T3 inherits the priority of T1 through T2.
  4.  

    Disadvantages of PIP

    Priority inheritance can lead to deadlock during the following situation

     

    Consider two tasks T1 and T2 uses two critical sections S1 and S2 in the following order

     

    T1: Lock S1; Lock S2;Unlock S2; Unlock S1

    T2: Lock S2; Lock S1;Unlock S1; Unlock S2

     

  5. Assume T1 is having higher priority over T2.  Suppose T2 starts execution at Time t0. At time t1, it locks S2.
  6. At time t2, T1 is initiated and it preempts T2 owing to its higher priority.
  7. At time t3, T1 locks S1.
  8. At time t4, T1 attempts to lock S2, which is being locked by T2. so T2 inherits the priority of T1 and starts executing,
  9. At time t5, T2 tries to lock S1, which is locked by T1.
  10. So both the tasks are now deadlocked.
  11.  

    This problem can be avoided by means of implementing priority Ceiling protocol

Simulation of Synchronous and Asynchronous counters

Requirements:

  • WARP
  • Active HDL
  • Cool Runner and Fitter CPLD Kit

Program for Asynchronous counter:
Library ieee;
Use ieee.std_logic_1164.all;
entity asyn_counter is
port (
clk: in BIT;
ce: in BIT;
clear: in BIT;
load: in BIT;
dir: in BIT;
p: in INTEGER range 0 to 255;
qd: out INTEGER range 0 to 255
);
end asyn_counter;
architecture asyn_counter of asyn_counter is
begin
process(clk,clear,load)
variable count : integer range 0 to 255;
begin
if(clear = ‘0’) then
count := 0;
elsif(load = ‘1’ and clear = ‘1’) then
if(ce = ‘1’ and dir = ‘0’) then
count := count + 0;
elsif(ce = ‘1’ and dir = ‘1’) then
count := count + 1;
end if;
end if;
qd <= count;
end process;
end asyn_counter;

Asynchronous counter

image 

 

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Synchronous Counter

Program for Synchronous Counter
library IEEE;
use IEEE.std_logic_1164.all;
entity syn_counter is
port (
clk: in STD_LOGIC;
ce: in STD_LOGIC;
clear: in STD_LOGIC;
load: in STD_LOGIC;
direction: in STD_LOGIC;
pre_value: in INTEGER range 0 to 15;
output: out INTEGER range 0 to 15
);
end syn_counter;
architecture syn_counter of syn_counter is
begin
process(clk)
variable temp: integer range 0 to 15;
begin
if(rising_edge(clk)) then
if(clear = ‘0’) then
temp := 0;
elsif(load = ‘1’) then
temp := pre_value;
elsif(ce=’1′ and direction = ‘0’) then
temp := (temp -1) mod 16;
elsif(ce = ‘1’ and direction = ‘1’) then
temp := (temp +1) mod 16;
end if;
end if;
output <= temp;
end process;
end syn_counter;

image

 

image

Simulation of Look Ahead Carry Generator

Requirements:

  • WARP
  • Active HDL

Design:

 

image

Program for the Look Ahead Carry Generator
library IEEE;
use IEEE.std_logic_1164.all;
entity look_ahead_carry is
port (
a: in STD_LOGIC_VECTOR (4 downto 1);
b: in STD_LOGIC_VECTOR (4 downto 1);
c0: in STD_LOGIC;
c: out STD_LOGIC_VECTOR (4 downto 1)
);
end look_ahead_carry;
architecture arch_look_ahead_carry of look_ahead_carry is
signal s1,s2,s3,s4,s5,s6,s7,s8:std_logic;
begin
s1 <= a(1) and b(1);
s2 <= a(1) or b(1);
s3 <= a(2) and b(2);
s4 <= a(2) or b(2);
s5 <= a(3) and b(3);
s6 <= a(3) or b(3);
s7 <= a(4) and b(4);
s8 <= a(4) or b(4);
c(1) <= s1 or (c0 and s2);
c(2) <= s3 or (s1 and s4) or (c0 and s2 and s4);
c(3) <= s5 or (s3 and s6) or (s1 and s4 and s6) or (c0 and s2 and s4 and s6);
c(4) <= s7 or (s5 and s8) or (s3 and s6 and s8) or (s1 and s4 and s6 and s8)
or (c0 and s2 and s4 and s6 and s8);
end arch_look_ahead_carry;

Waveform

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